SaTC: TTP: Medium: Hardware Intellectual Property Protection through Hybrid ASIC/TRAP Integrated Circuit Design

As the semiconductor industry transitioned from an in-house fabrication model to a third-party foundry model, it provided widespread access to cutting edge technology at affordable cost and accelerated development of advanced electronic circuits. At the same time, it introduced new concerns regarding protection of the intellectual property of these electronic circuits, whose blueprints must now be shared with globally distributed and potentially untrusted entities involved in the contemporary electronics supply chain. To address these concerns, this project is developing a methodology which enables redaction of proprietary or sensitive portions of an electronic circuit prior to fabrication and reinstatement upon receipt of the final product, thereby protecting the critical intellectual property from theft and/or malicious modification. By focusing on transitioning this technology to practice in collaboration with other academic institutions, industrial partners and federal laboratories, this project addresses the need for high technology-readiness level solutions as well as workforce development. Considering the pervasive development of electronics in every facet of modern life, including critical infrastructure, the objective of this project aligns with NSF's mission "to secure the national defense" and "to advance prosperity".

At a technical level, this project builds upon a novel Transistor-Level Programmable (TRAP) fabric which challenges conventional practices in reconfigurable computing by pushing granularity of post-fabrication programmability down to the transistor-level. Thereby, TRAP achieves significant reduction in area, performance and power consumption overhead over conventional Look-Up Table (LUT) based solutions, while at the same time presenting harder obstacles for brute-force or intelligent search-based reverse engineering attacks to overcome. To transition this technology to practice, this project is developing an ecosystem of design tools, training material and proof-of-concept silicon fabrication opportunities, to enable the use of untrusted facilities for manufacturing trusted electronic components while preventing unauthorized entities from being able to understand, use or copy sensitive hardware Intellectual Property.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Award Number: 2604733
Principal Investigator: Yiorgos Makris
Funds Obligated: $496,820
State: CA