IRES Track I:Collaborative Research:Application-Specific Asynchronous Deep Learning IC Design for Ultra-Low Power

This 3-year IRES Track I project recruits three cohorts of U.S. students to conduct research in China, with the major research goal as developing, fabricating, and testing an ultra-low power application-specific deep learning integrated circuit, and evaluating its performance through the integration with physical Internet-of-Things (IoT) edge computing devices. It brings together three research groups with unique expertise from University of Arkansas (ultra-low power asynchronous circuit design), University of South Alabama (context-aware memory design), and Peking University, China (deep learning algorithm development and optimization). The expected research outcomes will accelerate edge computing for a large variety of IoT applications such as advanced medical and elderly care systems, and self-driving vehicles. Each year six U.S. student participants work onsite at Peking University for eight weeks, leveraging the onsite research facilities. The multicultural, multidisciplinary nature of this project provides a unique training and career preparation opportunity for the participating students, including multidisciplinary discussion, teamwork, effective communication, and technical writing. The PIs continue their prior efforts in recruiting student participants from underrepresented and minority groups, leveraging their contacts and the existing mechanisms at each university. The research outcomes and the student experience will be disseminated nation-wide for benefiting the research community and encouraging more students to participate in similar programs.

Deep learning is transforming many modern Artificial Intelligence (AI) applications, in many of which deep learning has begun to exceed human performance. However, the superior performance of deep learning comes at the cost of extremely high computational complexity associated with large datasets. Therefore, deep learning algorithms are traditionally implemented in software and executed on powerful general-purpose cloud computing platforms. In contrast to the prevailing research in general-purpose counterparts, the application-specific deep learning IC has much lower power consumption, thereby ideal for integration with power-constrained IoT devices. This IRES project is to develop, fabricate, and test an ultra-low power deep learning integrated circuit (IC), and evaluate its performance through the integration with physical IoT edge computing devices. Technical innovations to be developed by the student participants include: 1) optimization of application-specific deep learning algorithms for alleviating the requirements of hardware implementation; 2) delay-insensitive asynchronous circuit design for substantially improved energy efficiency; and 3) context-aware memory development for power savings and low implementation cost. This project uniquely connects deep learning algorithm optimization, asynchronous circuit design, and memory optimization together to achieve a highly optimized system, which will benefit the semiconductor and AI societies at large by the revolutions in hardware-tailored deep learning algorithms and specialized computing hardware. It is expected that this research will demonstrate the advantages of application-specific deep learning hardware and layout the foundation of a new and promising direction for both academic research and industrial development.

This project is jointly funded by the Office of International Science and Engineering (OISE) and the Established Program to Stimulate Competitive Research (EPSCoR).

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Award Number: 2611766
Principal Investigator: Na Gong
Funds Obligated: $37,578
State: AL