I-Corps: Translation Potential of Tools for Simulation and Design Space Exploration For Chip Design and Hardware Acceleration

This I-Corps project focuses on the development of a fast and accurate simulation and design space exploration platform for chip design and hardware acceleration. Modern chip design workflows rely heavily on simulation tools that are either fast but inaccurate, or accurate but extremely slow, making it difficult for engineers to evaluate and optimize complex designs. These difficulties create a critical bottleneck in the development of high-performance computing systems, leading to increased costs, longer time-to-market, and underutilized hardware. This solution addresses these challenges by enabling engineers to simulate and evaluate chip designs significantly faster while maintaining high accuracy. This advance has the potential to improve productivity for thousands of engineers, shorten development cycles for new technologies, and reduce infrastructure needs. In doing so, the technology supports national efforts to advance semiconductor innovation, enhance energy-efficient computing, and strengthen domestic design capabilities in a rapidly evolving technology landscape.

This I-Corps project utilizes experiential learning coupled with a first-hand investigation of the industry ecosystem to assess the translation potential of the technology. This solution is based on the development of an intermediate representation–level simulation framework that provides cycle-level performance estimates without the need for slow and resource-intensive register-transfer level simulation. The approach decouples functionality from performance modeling, achieving over 99.9% accuracy with speed improvements of up to 200 times. The technology also supports rapid incremental exploration of hardware design parameters, such as memory partitioning, dataflow configuration, and communication buffering, enabling efficient architectural tuning. These capabilities are integrated into a modular and tool-compatible flow that benefits users by significantly accelerating feedback cycles and reducing dependence on manual edits or full synthesis. As a result, this solution empowers more scalable and informed decision-making in system design, helping researchers and engineers innovate faster and with greater efficiency.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Award Number: 2534120
Principal Investigator: Cong Hao
Funds Obligated: $50,000
State: GA