Conference: Low-Dimensional Materials and Electronics Conference

The semiconductor industry is rapidly approaching the fundamental limits of conventional scaling, creating an urgent need for transformative materials and integration strategies that can sustain progress in electronics and advanced artificial intelligence (AI) hardware. Low-dimensional (low-D) materials—metals, semiconductors, and insulators with one-dimensional features such as carbon nanotubes or atomically thin two-dimensional layers like molybdenum disulfide—offer a compelling pathway forward. With thicknesses of only a few atoms, these materials represent the ultimate size limit of electronic components and provide unique electrical, optical, and mechanical properties that surpass those of traditional semiconductor materials. However, while global investment in low-D technologies is accelerating, the United States is at risk of falling behind in both research leadership and commercialization. Addressing this challenge requires coordinated action across academia, industry, and government to identify critical scientific barriers, manufacturing needs, and integration opportunities. To catalyze this effort, a national conference will convene leading experts from universities, semiconductor companies, and national laboratories to establish a shared roadmap for accelerating and translating these materials from research labs into real technologies used by industry, thereby enabling the U.S. to secure leadership in next-generation semiconductor innovation and the hardware that will power future AI systems.

Low-dimensional materials such as carbon nanotubes (CNTs) and two-dimensional (2D) transition-metal dichalcogenides (TMDs), represent the fundamental physical limits of electronic materials, with characteristic thicknesses of only a few atomic layers. These systems exhibit several advantages over conventional semiconductors: (1) high electron and hole mobilities at thicknesses below the scaling limits of bulk silicon, which suffers mobility degradation below ~3 nm; (2) compatibility with heterogeneous integration approaches, as many 2D materials can be synthesized via van der Waals epitaxy directly on amorphous substrates or transferred as isolated layers or heterostructures; and (3) an exceptionally large design space, with over a thousand known 2D compounds, hundreds of which possess electronic bandgaps between ~0.5–3 eV. Despite recent academic progress, major barriers remain in synthesis scalability, defect and doping control, interface engineering, metrology at atomic length scales, and device architectures that provide clear performance, energy-efficiency, or manufacturability advantages relative to advanced silicon electronics. These gaps must be addressed for effective lab-to-fab translation. The 2026 NSF Low-Dimensional Semiconductor Conference aims to define a national strategic roadmap by convening U.S. leaders across academia, industry, and government laboratories. The agenda will focus on synthesis challenges, stability of dopants and defects, 3D integration pathways, metrology methods compatible with industry toolsets, emerging quantum and transport phenomena relevant to device engineering, and benchmarks for evaluating system-level competitiveness. Outcomes will include a report identifying critical research directions, estimated timelines and investments required for commercialization, and recommendations for structuring a coordinated national effort to ensure U.S. leadership in low-D materials and their semiconductor applications.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Award Number: 2549841
Principal Investigator: Eric Pop
Funds Obligated: $299,596
State: CA